Camera ISP and AI ISP IP cores for FPGA and ASIC

ASICFPGA (Markham, Ontario, Canada, since 2007) develops camera image signal processor (ISP) IP cores for AMD/Xilinx FPGA and ASIC designs, delivered as Verilog source or FPGA netlist with documentation and testbench. The ISP takes Bayer data from the image sensor and performs defect correction, lens shading correction, demosaicing, 2D/3D noise reduction, color correction, gamma, HDR/WDR, edge enhancement and AE/AWB statistics, at 1, 2 or 4 pixels per clock up to 8K. The Verilog RTL is not tied to one FPGA vendor and can be ported to other FPGA families, with porting support from ASICFPGA.

The AI 2D+3DNR core is a deep-learning denoiser implemented directly in RTL. It runs in the FPGA fabric next to the ISP — no DPU, Vitis AI, NPU or GPU is needed — and is verified on the AMD Kria KV260 at 1920x1080, 30 fps with a Sony IMX678 sensor. See the evaluation kit.