ASICFPGA introduces AI 2D+3DNR, a deep-learning denoiser IP core that runs in FPGA logic without an NPU

Nov. 13, 2026

ASICFPGA introduces AI 2D+3DNR, a deep-learning denoiser IP core that runs in FPGA logic without an NPU

Deep-learning spatial and temporal noise reduction with learned motion compensation, implemented in Verilog RTL. Verified at 1920x1080, 30 fps on the AMD Kria KV260 with a Sony IMX678 sensor. Strength is set automatically from the sensor gain.

ASICFPGA, a supplier of camera image signal processor (ISP) IP cores, introduces AI 2D+3DNR, a deep-learning noise reduction IP core for very low-light cameras. The neural network is implemented directly in FPGA logic, so it runs next to the camera ISP without a DPU, NPU, GPU or any other AI accelerator. ASICFPGA also offers ASICFPGA IQ Tool, software that measures camera image quality from one photo of a test chart.

Deep-learning noise reduction in FPGA logic, without an AI accelerator

AI 2D+3DNR is a separate IP that customers who need the best low-light image quality can use in place of the Advanced 2D+3DNR included in the ASICFPGA ISP. Running a neural network on an FPGA usually requires a DPU or NPU accelerator and its own tool flow. AI 2D+3DNR is written in Verilog RTL with fixed-point weights stored in on-chip memory, and uses only FPGA logic, DSP blocks and on-chip RAM, so it is integrated like any other ISP block.

The core removes spatial and temporal noise together in the Bayer domain while keeping edges and fine texture. Deep-learning motion compensation aligns the previous frame to the current frame before temporal filtering, which reduces ghosting and keeps detail on moving objects. The strength follows the sensor gain, so no manual tuning is needed from normal light to very low light.

Together with the full ASICFPGA camera ISP, AI 2D+3DNR has been verified on the AMD Kria KV260 (Zynq UltraScale+ MPSoC) at 1920x1080, 30 fps with a Sony IMX678 image sensor. For other image sensors, ASICFPGA measures the sensor noise at each gain and adapts the network. Comparison videos for several scenes and sensor gains are available at www.asicfpga.com/dnr_ai.

Figure 1. Simulated low-light noisy input (left) and AI 2D+3DNR output (right): street, accordion player and portrait. Clean videos were converted to IMX678 RAW with the sensor noise at 48 dB gain (extrapolated from noise measured at 42 dB) and processed by the same ISP.

Complete camera ISP IP core

The ASICFPGA camera ISP IP core takes Bayer data from the image sensor and performs HDR/WDR, lens shading correction, defect pixel correction, 2D/3D noise reduction, demosaicing, color correction, gamma, RGB to YUV conversion, edge enhancement, saturation/contrast/brightness adjustment, and AE/AWB/AF statistics with histograms, in the order shown in Figure 2. It processes 1, 2 or 4 pixels per clock up to 8K and provides AXI4-Lite and AXI4-Stream interfaces. The HDR core merges two or three exposures for up to 120 dB dynamic range.

Noise reduction is provided by the Advanced 2D+3DNR (1080p60 and 2160p60) as standard. Customers for whom low-light noise matters most can use AI 2D+3DNR (1920x1080, 30 fps) in the same position as a separate IP (the "one of" block in Figure 2).

Figure 2. Processing pipeline of the ASICFPGA camera ISP IP core. The noise reduction stage uses either the standard Advanced 2D+3DNR or the optional AI 2D+3DNR.

RTL not tied to one FPGA vendor

All IP cores are delivered as Verilog RTL source or FPGA netlist, with documentation and a testbench. The RTL is not tied to one FPGA vendor and can be ported to other FPGA families, with porting support from ASICFPGA. For high volumes, the same RTL can be used in an ASIC.

Evaluation kit

The ISP and AI 2D+3DNR cores can be evaluated on the AMD Kria KV260 Vision AI Starter Kit with the ASICFPGA Sony IMX678 sensor module. The evaluation bitstream and software are available on request.

ASICFPGA IQ Tool: camera image quality from one photo of a test chart

ASICFPGA also offers ASICFPGA IQ Tool, image quality measurement software. Open a photo of a test chart and the program finds the chart by itself and reports the results in graphs and tables: sharpness (slanted-edge MTF, MTF50), texture (dead leaves), noise and SNR, tone, color error (ΔE00), white balance, distortion, shading, flare and dynamic range.

Unlike most chart software, IQ Tool needs no chart selection and no hand-drawn regions: a neural network finds the chart and places every measurement region, even when the chart is tilted, small or in a busy scene. A shot check tells the user whether the photo should be retaken (chart too small, tilted, over-exposed and so on) and how to fix it.

Figure 4. IQ Tool finds the chart and places every measurement region (slanted edges, stars, color patches, grey patches, wedges) by itself.

The program prints 16 ASICFPGA test charts on paper from 8x8 inch to A0 or shows them full screen on a monitor, so no chart purchase is needed to start; it also reads common commercial charts such as ISO 12233 e-SFR and ColorChecker 24. It opens raw Bayer and 16-bit images, saves results as CSV, JSON and PNG, and compares results before and after a change in the ISP, lens or firmware.

IQ Tool runs on Windows 10/11 (an NVIDIA GPU is used if present). A 30-day trial is available after signing up at www.asicfpga.com/iqtool.

Figure 5. IQ Tool sharpness (MTF) results.

About ASICFPGA

Founded in 2007, ASICFPGA develops image processing IP cores for FPGA and ASIC, providing camera ISP solutions for customers who integrate them into SoC, ASIC and FPGA designs.

Comparison videos and details of AI 2D+3DNR ASICFPGA IQ Tool - sign up and download